Integrated circuits typically include a plurality of semiconductor devices and interconnect wiring. Networks of metal interconnect wiring are often used to connect the semiconductor devices. Multiple levels of metal interconnect wiring above the semiconductor portion of the substrate are connected together to form a back-end-of-the-line (“BEOL”) interconnect structure. Within such a structure, metal lines run parallel to the substrate and conductive vias run perpendicular to the substrate. The conductive vias typically interconnect the different levels of the metal wiring levels.
Two developments have contributed to increased performance of contemporary integrated circuits due to improved interconnects. One such development is the use of copper as the interconnect metal of the BEOL interconnect structure. Copper is advantageous because it has a higher conductivity compared with the other traditionally used interconnect metals, such as, for example, aluminum. A second development is the employment within the BEOL interconnect structure of a low dielectric constant (low k) dielectric material as the interlayer dielectric (ILD) layer or layers. By “low k,” it is meant that the dielectric constant of a particular dielectric material is less than that of silicon dioxide.
When copper is used as the metal in the interconnect wiring layers, a dielectric barrier layer or “dielectric cap” is typically required between the copper features and the ILD to prevent copper from diffusing into certain types of ILD materials so as to prevent the copper from damaging the insulative electrical properties of the dielectric. Therefore, the typical fabrication process involves depositing copper into trenches formed in the interlayer dielectric, planarizing the copper, and etching the copper to recess it within the respective trenches before a dielectric cap is formed over the copper and within the trench. This process is time consuming and can present a bottleneck in fabrication processing.
Accordingly, it is desirable to provide methods for fabricating integrated circuits that form metal interconnect structures more efficiently. Also, it is desirable to provide methods for fabricating integrated circuits that use chemical mechanical planarization (CMP) to recess metal within trenches. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.